Synopsys Design Compiler Tutorial 2021 -

You can launch DC in two primary modes:

################################################################### # Synopsys Design Compiler Automation Script ################################################################### # 1. Setup paths and directories file mkdir reports file mkdir outputs # 2. Read Design analyze -format verilog my_alu.v control_unit.v top_module.v elaborate top_module current_design top_module # 3. Link and Check link check_design # 4. Apply Constraints create_clock -name sys_clk -period 10.0 [get_ports clk] set_clock_uncertainty 0.20 [get_clocks sys_clk] set_input_delay 2.5 -clock sys_clk [remove_from_collection [all_inputs] [get_ports clk]] set_output_delay 2.5 -clock sys_clk [all_outputs] set_driving_cell -lib_cell BUFX4 [remove_from_collection [all_inputs] [get_ports clk]] set_load 0.2 [all_outputs] # 5. Compile compile_ultra -gate_clock # 6. Generate Reports report_design > reports/design_summary.rpt report_area -hierarchy > reports/area_summary.rpt report_timing -max_paths 5 > reports/timing_worst_paths.rpt report_constraint -all_violators > reports/violations.rpt # 7. Export Outputs change_names -rules verilog -hierarchy write -format verilog -hierarchy -output outputs/top_module_netlist.v write_sdc outputs/top_module.sdc echo "========================================" echo "SYNTHESIS FLOW COMPLETED SUCCESSFULLY!" echo "========================================" exit Use code with caution. Executing the Script via Command Line synopsys design compiler tutorial 2021

# Create a primary clock named 'sys_clk' with a 10ns period on port 'clk' create_clock -name sys_clk -period 10.0 [get_ports clk] # Model clock jitter and routing delay (skew) using uncertainty set_clock_uncertainty 0.25 [get_clocks sys_clk] # Define clock transition times (slew rate) set_clock_transition 0.15 [get_clocks sys_clk] Use code with caution. Input and Output Delays You can launch DC in two primary modes:

Compile the design. The 2021 version heavily utilizes the ( -map_effort high ) to accurately estimate wire loads. Link and Check link check_design # 4

If check_design returns errors regarding visual or open pins, resolve them in the RTL code before proceeding. Step 3: Applying Timing and Area Constraints

At its core, logic synthesis is the process of converting a Register Transfer Level (RTL) description of your hardware (in Verilog or VHDL) into an optimized, technology-specific gate-level netlist. This netlist is composed of standard cells from a foundry's technology library and is ready for the physical design flow (place and route).

# Model the driving strength of an external input port using a library buffer set_driving_cell -lib_cell BUFX2 [get_ports data_in] # Define the maximum capacitive load allowed on output ports set_load 0.05 [get_ports data_out] # Set the target design area to 0 (instructs DC to make the design as small as possible) set_max_area 0 Use code with caution. 5. Optimization and Compiling